OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 101

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 Added sample application for local config processor ghutchis 4864d 23h /tv80/trunk/rtl/
100 Changed do to dout in tv80n, checked in fix for flags bug ghutchis 4895d 22h /tv80/trunk/rtl/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5311d 19h /tv80/trunk/rtl/
89 RTL and environment fixes for nmi bug ghutchis 5331d 22h /tv80/trunk/rtl/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5333d 13h /tv80/trunk/rtl/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5348d 20h /tv80/trunk/rtl/
84 New directory structure. root 5572d 08h /tv80/trunk/rtl/
83 Some fixes from Guy-- replace case with casex. hharte 5645d 14h /trunk/rtl/
82 Clean up spacing hharte 5655d 10h /trunk/rtl/
81 Initial version of TV80 Wishbone Wrapper hharte 5655d 11h /trunk/rtl/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6754d 23h /trunk/rtl/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6798d 01h /trunk/rtl/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6909d 02h /trunk/rtl/
71 Ported UART from T80 ghutchis 6982d 00h /trunk/rtl/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic
ghutchis 7040d 20h /trunk/rtl/
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.
ghutchis 7075d 23h /trunk/rtl/
58 Made TX path async
Made TX clock input instead of output
ghutchis 7115d 11h /trunk/rtl/
52 Added simple GMII-like interface for testing ghutchis 7117d 17h /trunk/rtl/
45 Added negedge version of top ghutchis 7132d 20h /trunk/rtl/
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7160d 18h /trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.