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[/] [tv80/] [trunk/] [rtl/] - Rev 82

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Rev Log message Author Age Path
82 Clean up spacing hharte 5780d 22h /tv80/trunk/rtl/
81 Initial version of TV80 Wishbone Wrapper hharte 5780d 22h /tv80/trunk/rtl/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6880d 11h /tv80/trunk/rtl/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6923d 12h /tv80/trunk/rtl/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 7034d 13h /tv80/trunk/rtl/
71 Ported UART from T80 ghutchis 7107d 12h /tv80/trunk/rtl/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic		 ghutchis 7166d 07h /tv80/trunk/rtl/
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.		 ghutchis 7201d 11h /tv80/trunk/rtl/
58 Made TX path async
Made TX clock input instead of output		 ghutchis 7240d 22h /tv80/trunk/rtl/
52 Added simple GMII-like interface for testing ghutchis 7243d 05h /tv80/trunk/rtl/
45 Added negedge version of top ghutchis 7258d 08h /tv80/trunk/rtl/
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7286d 06h /tv80/trunk/rtl/
24 tv80s.v ghutchis 7314d 22h /tv80/trunk/rtl/
23 Completed conversion to one-hot encoding ghutchis 7327d 12h /tv80/trunk/rtl/
22 Changed starting state for one-hot tstate ghutchis 7327d 12h /tv80/trunk/rtl/
21 Replaced encoded states with one-hot ghutchis 7328d 12h /tv80/trunk/rtl/
4 Removed obsolete top level ghutchis 7456d 09h /tv80/trunk/rtl/
2 Initial commit ghutchis 7456d 12h /tv80/trunk/rtl/

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