URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 84

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Rev	Log message	Author	Age	Path
84	New directory structure.	root	5689d 04h	/tv80/trunk/rtl/
83	Some fixes from Guy-- replace case with casex.	hharte	5762d 11h	/trunk/rtl/
82	Clean up spacing	hharte	5772d 07h	/trunk/rtl/
81	Initial version of TV80 Wishbone Wrapper	hharte	5772d 07h	/trunk/rtl/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6871d 19h	/trunk/rtl/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6914d 21h	/trunk/rtl/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	7025d 22h	/trunk/rtl/
71	Ported UART from T80	ghutchis	7098d 21h	/trunk/rtl/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7157d 16h	/trunk/rtl/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7192d 20h	/trunk/rtl/
58	Made TX path async Made TX clock input instead of output	ghutchis	7232d 07h	/trunk/rtl/
52	Added simple GMII-like interface for testing	ghutchis	7234d 13h	/trunk/rtl/
45	Added negedge version of top	ghutchis	7249d 17h	/trunk/rtl/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7277d 14h	/trunk/rtl/
24	tv80s.v	ghutchis	7306d 06h	/trunk/rtl/
23	Completed conversion to one-hot encoding	ghutchis	7318d 20h	/trunk/rtl/
22	Changed starting state for one-hot tstate	ghutchis	7318d 20h	/trunk/rtl/
21	Replaced encoded states with one-hot	ghutchis	7319d 21h	/trunk/rtl/
4	Removed obsolete top level	ghutchis	7447d 18h	/trunk/rtl/
2	Initial commit	ghutchis	7447d 21h	/trunk/rtl/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 84

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