URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 85

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Rev	Log message	Author	Age	Path
84	New directory structure.	root	5604d 03h	/tv80/trunk/rtl/
83	Some fixes from Guy-- replace case with casex.	hharte	5677d 09h	/trunk/rtl/
82	Clean up spacing	hharte	5687d 05h	/trunk/rtl/
81	Initial version of TV80 Wishbone Wrapper	hharte	5687d 06h	/trunk/rtl/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6786d 18h	/trunk/rtl/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6829d 20h	/trunk/rtl/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6940d 21h	/trunk/rtl/
71	Ported UART from T80	ghutchis	7013d 19h	/trunk/rtl/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7072d 15h	/trunk/rtl/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7107d 18h	/trunk/rtl/
58	Made TX path async Made TX clock input instead of output	ghutchis	7147d 06h	/trunk/rtl/
52	Added simple GMII-like interface for testing	ghutchis	7149d 12h	/trunk/rtl/
45	Added negedge version of top	ghutchis	7164d 15h	/trunk/rtl/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7192d 13h	/trunk/rtl/
24	tv80s.v	ghutchis	7221d 05h	/trunk/rtl/
23	Completed conversion to one-hot encoding	ghutchis	7233d 19h	/trunk/rtl/
22	Changed starting state for one-hot tstate	ghutchis	7233d 19h	/trunk/rtl/
21	Replaced encoded states with one-hot	ghutchis	7234d 20h	/trunk/rtl/
4	Removed obsolete top level	ghutchis	7362d 17h	/trunk/rtl/
2	Initial commit	ghutchis	7362d 20h	/trunk/rtl/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 85

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