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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 44

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Rev Log message Author Age Path
44 fixed more typo bugs gorban 8304d 21h /uart16550/tags/asyst_3/rtl/verilog/
43 lsr1r error fixed. mohor 8305d 04h /uart16550/tags/asyst_3/rtl/verilog/
42 ti_int_pnd error fixed. mohor 8305d 04h /uart16550/tags/asyst_3/rtl/verilog/
41 ti_int_d error fixed. mohor 8305d 04h /uart16550/tags/asyst_3/rtl/verilog/
40 Synthesis bugs fixed. Some other minor changes gorban 8307d 06h /uart16550/tags/asyst_3/rtl/verilog/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8309d 04h /uart16550/tags/asyst_3/rtl/verilog/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8310d 01h /uart16550/tags/asyst_3/rtl/verilog/
36 no message mohor 8315d 09h /uart16550/tags/asyst_3/rtl/verilog/
35 Fixes to break and timeout conditions gorban 8317d 04h /uart16550/tags/asyst_3/rtl/verilog/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8319d 02h /uart16550/tags/asyst_3/rtl/verilog/
33 Small synopsis fixes gorban 8328d 09h /uart16550/tags/asyst_3/rtl/verilog/
32 Changes data_out to be synchronous again as it should have been. gorban 8329d 03h /uart16550/tags/asyst_3/rtl/verilog/
31 small fix gorban 8329d 23h /uart16550/tags/asyst_3/rtl/verilog/
30 Modified port names again gorban 8384d 03h /uart16550/tags/asyst_3/rtl/verilog/
29 Things connected to parity changed.
Clock devider changed.		 mohor 8384d 22h /uart16550/tags/asyst_3/rtl/verilog/
28 FIFO was not cleared after the data was read bug fixed. mohor 8385d 10h /uart16550/tags/asyst_3/rtl/verilog/
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8386d 03h /uart16550/tags/asyst_3/rtl/verilog/

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