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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 69

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Rev Log message Author Age Path
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8256d 15h /uart16550/tags/asyst_3/rtl/verilog/
68 lsr[7] was not showing overrun errors. mohor 8259d 22h /uart16550/tags/asyst_3/rtl/verilog/
67 Missing declaration of rf_push_q fixed. mohor 8266d 22h /uart16550/tags/asyst_3/rtl/verilog/
66 rx push changed to be only one cycle wide. mohor 8266d 22h /uart16550/tags/asyst_3/rtl/verilog/
65 Warnings fixed (unused signals removed). mohor 8268d 03h /uart16550/tags/asyst_3/rtl/verilog/
64 Warnings cleared. mohor 8268d 03h /uart16550/tags/asyst_3/rtl/verilog/
63 Synplicity was having troubles with the comment. mohor 8268d 04h /uart16550/tags/asyst_3/rtl/verilog/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8269d 02h /uart16550/tags/asyst_3/rtl/verilog/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8269d 21h /uart16550/tags/asyst_3/rtl/verilog/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8270d 01h /uart16550/tags/asyst_3/rtl/verilog/
59 MSR register fixed. mohor 8272d 22h /uart16550/tags/asyst_3/rtl/verilog/
58 After reset modem status register MSR should be reset. mohor 8273d 01h /uart16550/tags/asyst_3/rtl/verilog/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8274d 01h /uart16550/tags/asyst_3/rtl/verilog/
56 thre irq should be cleared only when being source of interrupt. mohor 8274d 01h /uart16550/tags/asyst_3/rtl/verilog/
55 some synthesis bugs fixed gorban 8274d 13h /uart16550/tags/asyst_3/rtl/verilog/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8275d 02h /uart16550/tags/asyst_3/rtl/verilog/
53 Scratch register define added. mohor 8276d 02h /uart16550/tags/asyst_3/rtl/verilog/
52 Scratch register added gorban 8276d 15h /uart16550/tags/asyst_3/rtl/verilog/
51 Igor fixed break condition bugs gorban 8276d 15h /uart16550/tags/asyst_3/rtl/verilog/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8280d 20h /uart16550/tags/asyst_3/rtl/verilog/

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