OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 73

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 major bug in 32-bit mode that prevented register access fixed. gorban 8190d 11h /uart16550/tags/asyst_3/rtl/verilog/
71 Removed confusing comment gorban 8215d 07h /uart16550/tags/asyst_3/rtl/verilog/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8220d 16h /uart16550/tags/asyst_3/rtl/verilog/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8229d 06h /uart16550/tags/asyst_3/rtl/verilog/
68 lsr[7] was not showing overrun errors. mohor 8232d 14h /uart16550/tags/asyst_3/rtl/verilog/
67 Missing declaration of rf_push_q fixed. mohor 8239d 14h /uart16550/tags/asyst_3/rtl/verilog/
66 rx push changed to be only one cycle wide. mohor 8239d 14h /uart16550/tags/asyst_3/rtl/verilog/
65 Warnings fixed (unused signals removed). mohor 8240d 18h /uart16550/tags/asyst_3/rtl/verilog/
64 Warnings cleared. mohor 8240d 19h /uart16550/tags/asyst_3/rtl/verilog/
63 Synplicity was having troubles with the comment. mohor 8240d 19h /uart16550/tags/asyst_3/rtl/verilog/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8241d 18h /uart16550/tags/asyst_3/rtl/verilog/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8242d 12h /uart16550/tags/asyst_3/rtl/verilog/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8242d 17h /uart16550/tags/asyst_3/rtl/verilog/
59 MSR register fixed. mohor 8245d 14h /uart16550/tags/asyst_3/rtl/verilog/
58 After reset modem status register MSR should be reset. mohor 8245d 17h /uart16550/tags/asyst_3/rtl/verilog/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8246d 17h /uart16550/tags/asyst_3/rtl/verilog/
56 thre irq should be cleared only when being source of interrupt. mohor 8246d 17h /uart16550/tags/asyst_3/rtl/verilog/
55 some synthesis bugs fixed gorban 8247d 05h /uart16550/tags/asyst_3/rtl/verilog/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8247d 18h /uart16550/tags/asyst_3/rtl/verilog/
53 Scratch register define added. mohor 8248d 18h /uart16550/tags/asyst_3/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.