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[/] [uart16550/] [tags/] [rel_1/] - Rev 108

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Rev Log message Author Age Path
106 New directory structure. root 5570d 02h /uart16550/tags/rel_1/
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8145d 20h /tags/rel_1/
75 Endian define added. Big Byte Endian is selected by default. mohor 8145d 20h /trunk/
74 tf_overrun signal was disabled since it was not used gorban 8150d 21h /trunk/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8157d 20h /trunk/
72 UART PHY added. Files are fully operational, working on HW. mohor 8171d 04h /trunk/
71 Removed confusing comment gorban 8182d 16h /trunk/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8188d 01h /trunk/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8196d 16h /trunk/
68 lsr[7] was not showing overrun errors. mohor 8199d 23h /trunk/
67 Missing declaration of rf_push_q fixed. mohor 8206d 23h /trunk/
66 rx push changed to be only one cycle wide. mohor 8206d 23h /trunk/
65 Warnings fixed (unused signals removed). mohor 8208d 04h /trunk/
64 Warnings cleared. mohor 8208d 04h /trunk/
63 Synplicity was having troubles with the comment. mohor 8208d 05h /trunk/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8209d 04h /trunk/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8209d 22h /trunk/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8210d 02h /trunk/
59 MSR register fixed. mohor 8212d 23h /trunk/
58 After reset modem status register MSR should be reset. mohor 8213d 02h /trunk/

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