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[/] [uart16550/] [tags/] [rel_1/] [rtl/] - Rev 106

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Rev	Log message	Author	Age	Path
106	New directory structure.	root	5570d 11h	/uart16550/tags/rel_1/rtl/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8146d 04h	/uart16550/tags/rel_1/rtl/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8146d 04h	/uart16550/tags/rel_1/rtl/
74	tf_overrun signal was disabled since it was not used	gorban	8151d 05h	/uart16550/tags/rel_1/rtl/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8158d 04h	/uart16550/tags/rel_1/rtl/
71	Removed confusing comment	gorban	8183d 00h	/uart16550/tags/rel_1/rtl/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8188d 09h	/uart16550/tags/rel_1/rtl/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8197d 00h	/uart16550/tags/rel_1/rtl/
68	lsr[7] was not showing overrun errors.	mohor	8200d 07h	/uart16550/tags/rel_1/rtl/
67	Missing declaration of rf_push_q fixed.	mohor	8207d 07h	/uart16550/tags/rel_1/rtl/
66	rx push changed to be only one cycle wide.	mohor	8207d 07h	/uart16550/tags/rel_1/rtl/
65	Warnings fixed (unused signals removed).	mohor	8208d 12h	/uart16550/tags/rel_1/rtl/
64	Warnings cleared.	mohor	8208d 13h	/uart16550/tags/rel_1/rtl/
63	Synplicity was having troubles with the comment.	mohor	8208d 13h	/uart16550/tags/rel_1/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8209d 12h	/uart16550/tags/rel_1/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8210d 06h	/uart16550/tags/rel_1/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8210d 10h	/uart16550/tags/rel_1/rtl/
59	MSR register fixed.	mohor	8213d 07h	/uart16550/tags/rel_1/rtl/
58	After reset modem status register MSR should be reset.	mohor	8213d 11h	/uart16550/tags/rel_1/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8214d 10h	/uart16550/tags/rel_1/rtl/

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[/] [uart16550/] [tags/] [rel_1/] [rtl/] - Rev 106

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