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Rev Log message Author Age Path
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7560d 15h /uart16550/tags/rel_2/
91 Removed files due to new complete testbench. tadejm 7561d 06h /uart16550/tags/rel_2/
90 Add Flextronics header avisha 7563d 13h /uart16550/tags/rel_2/
89 adjusted comment + define dries 7643d 18h /uart16550/tags/rel_2/
88 added clearing the receiver fifo statuses on resets gorban 7706d 07h /uart16550/tags/rel_2/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7736d 09h /uart16550/tags/rel_2/
86 restored include for uart_defines.v in uart_test.v gorban 8006d 13h /uart16550/tags/rel_2/
85 Updated documentation to include latest changes. gorban 8040d 05h /uart16550/tags/rel_2/
84 The uart_defines.v file is included again in sources. gorban 8053d 04h /uart16550/tags/rel_2/
83 Reverted to include uart_defines.v file in other files again. gorban 8053d 04h /uart16550/tags/rel_2/
82 Updated to work with latest core. gorban 8060d 02h /uart16550/tags/rel_2/
81 Added lastest additions. gorban 8060d 03h /uart16550/tags/rel_2/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 8060d 03h /uart16550/tags/rel_2/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 8060d 03h /uart16550/tags/rel_2/
75 Endian define added. Big Byte Endian is selected by default. mohor 8213d 09h /uart16550/tags/rel_2/
74 tf_overrun signal was disabled since it was not used gorban 8218d 10h /uart16550/tags/rel_2/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8225d 09h /uart16550/tags/rel_2/
72 UART PHY added. Files are fully operational, working on HW. mohor 8238d 17h /uart16550/tags/rel_2/
71 Removed confusing comment gorban 8250d 05h /uart16550/tags/rel_2/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8255d 14h /uart16550/tags/rel_2/

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