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[/] [uart16550/] [tags/] [rel_2/] [bench/] - Rev 108

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Rev Log message Author Age Path
106 New directory structure. root 5587d 04h /uart16550/tags/rel_2/bench/
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7396d 10h /uart16550/tags/rel_2/bench/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7396d 10h /uart16550/tags/rel_2/bench/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7396d 11h /uart16550/tags/rel_2/bench/
91 Removed files due to new complete testbench. tadejm 7510d 19h /uart16550/tags/rel_2/bench/
86 restored include for uart_defines.v in uart_test.v gorban 7956d 02h /uart16550/tags/rel_2/bench/
83 Reverted to include uart_defines.v file in other files again. gorban 8002d 17h /uart16550/tags/rel_2/bench/
72 UART PHY added. Files are fully operational, working on HW. mohor 8188d 06h /uart16550/tags/rel_2/bench/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8240d 17h /uart16550/tags/rel_2/bench/
38 small update to test interrupts gorban 8266d 20h /uart16550/tags/rel_2/bench/
17 added empty directories for the required structure. gorban 8353d 20h /uart16550/tags/rel_2/bench/
14 gorban 8353d 22h /uart16550/tags/rel_2/bench/

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