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[/] [uart16550/] [trunk/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5724d 23h /uart16550/trunk/
105 Timeout interrupt should be generated only when there is at least ony
character in the fifo.		 igorm 7294d 00h /trunk/
103 Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. tadejm 7450d 19h /trunk/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7478d 21h /trunk/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7478d 22h /trunk/
99 Added synchronizer flops for RX input. tadejm 7478d 22h /trunk/
98 Added to synchronize RX input to Wishbone clock. tadejm 7478d 22h /trunk/
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7534d 05h /trunk/
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7534d 05h /trunk/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7534d 06h /trunk/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7534d 06h /trunk/
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7647d 23h /trunk/
91 Removed files due to new complete testbench. tadejm 7648d 14h /trunk/
90 Add Flextronics header avisha 7650d 21h /trunk/
89 adjusted comment + define dries 7731d 02h /trunk/
88 added clearing the receiver fifo statuses on resets gorban 7793d 15h /trunk/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7823d 17h /trunk/
86 restored include for uart_defines.v in uart_test.v gorban 8093d 21h /trunk/
85 Updated documentation to include latest changes. gorban 8127d 13h /trunk/
84 The uart_defines.v file is included again in sources. gorban 8140d 12h /trunk/

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