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[/] [uart16550/] [trunk/] - Rev 54

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Rev Log message Author Age Path
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8253d 02h /uart16550/trunk/
53 Scratch register define added. mohor 8254d 02h /uart16550/trunk/
52 Scratch register added gorban 8254d 15h /uart16550/trunk/
51 Igor fixed break condition bugs gorban 8254d 16h /uart16550/trunk/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8258d 21h /uart16550/trunk/
49 committed the debug interface file gorban 8260d 14h /uart16550/trunk/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8261d 14h /uart16550/trunk/
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8266d 16h /uart16550/trunk/
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8267d 13h /uart16550/trunk/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8268d 14h /uart16550/trunk/
44 fixed more typo bugs gorban 8282d 13h /uart16550/trunk/
43 lsr1r error fixed. mohor 8282d 20h /uart16550/trunk/
42 ti_int_pnd error fixed. mohor 8282d 20h /uart16550/trunk/
41 ti_int_d error fixed. mohor 8282d 21h /uart16550/trunk/
40 Synthesis bugs fixed. Some other minor changes gorban 8284d 23h /uart16550/trunk/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8286d 20h /uart16550/trunk/
38 small update to test interrupts gorban 8287d 17h /uart16550/trunk/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8287d 18h /uart16550/trunk/
36 no message mohor 8293d 01h /uart16550/trunk/
35 Fixes to break and timeout conditions gorban 8294d 20h /uart16550/trunk/

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