URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [bench/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5732d 19h	/uart16550/trunk/bench/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7542d 01h	/trunk/bench/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7542d 01h	/trunk/bench/
91	Removed files due to new complete testbench.	tadejm	7656d 09h	/trunk/bench/
86	restored include for uart_defines.v in uart_test.v	gorban	8101d 17h	/trunk/bench/
83	Reverted to include uart_defines.v file in other files again.	gorban	8148d 08h	/trunk/bench/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8333d 20h	/trunk/bench/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8386d 08h	/trunk/bench/
38	small update to test interrupts	gorban	8412d 11h	/trunk/bench/
17	added empty directories for the required structure.	gorban	8499d 10h	/trunk/bench/
14		gorban	8499d 13h	/trunk/bench/