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[/] [uart16550/] [trunk/] [rtl/] - Rev 64

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Rev Log message Author Age Path
64 Warnings cleared. mohor 8276d 02h /uart16550/trunk/rtl/
63 Synplicity was having troubles with the comment. mohor 8276d 03h /uart16550/trunk/rtl/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8277d 01h /uart16550/trunk/rtl/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8277d 19h /uart16550/trunk/rtl/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8278d 00h /uart16550/trunk/rtl/
59 MSR register fixed. mohor 8280d 21h /uart16550/trunk/rtl/
58 After reset modem status register MSR should be reset. mohor 8281d 00h /uart16550/trunk/rtl/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8282d 00h /uart16550/trunk/rtl/
56 thre irq should be cleared only when being source of interrupt. mohor 8282d 00h /uart16550/trunk/rtl/
55 some synthesis bugs fixed gorban 8282d 12h /uart16550/trunk/rtl/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8283d 01h /uart16550/trunk/rtl/
53 Scratch register define added. mohor 8284d 01h /uart16550/trunk/rtl/
52 Scratch register added gorban 8284d 14h /uart16550/trunk/rtl/
51 Igor fixed break condition bugs gorban 8284d 14h /uart16550/trunk/rtl/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8288d 19h /uart16550/trunk/rtl/
49 committed the debug interface file gorban 8290d 13h /uart16550/trunk/rtl/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8291d 12h /uart16550/trunk/rtl/
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8296d 14h /uart16550/trunk/rtl/
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8297d 12h /uart16550/trunk/rtl/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8298d 12h /uart16550/trunk/rtl/

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