URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 30

Rev	Log message	Author	Age	Path
30	Modified port names again	gorban	8356d 09h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8357d 03h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8357d 16h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8358d 08h	/uart16550/trunk/rtl/verilog/