URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 35

Rev	Log message	Author	Age	Path
35	Fixes to break and timeout conditions	gorban	8316d 15h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8318d 14h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8327d 21h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8328d 14h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8329d 10h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8383d 15h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8384d 10h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8384d 22h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8385d 15h	/uart16550/trunk/rtl/verilog/