URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 36

Rev	Log message	Author	Age	Path
36	no message	mohor	8417d 22h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8419d 17h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8421d 15h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8430d 22h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8431d 16h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8432d 11h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8486d 16h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8487d 11h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8487d 23h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8488d 16h	/uart16550/trunk/rtl/verilog/