URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 37

Rev	Log message	Author	Age	Path
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8377d 11h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8382d 19h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8384d 13h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8386d 12h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8395d 19h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8396d 12h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8397d 08h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8451d 13h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8452d 08h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8452d 20h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8453d 13h	/uart16550/trunk/rtl/verilog/