URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 42

Rev	Log message	Author	Age	Path
42	ti_int_pnd error fixed.	mohor	8304d 14h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8304d 14h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8306d 16h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8308d 14h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8309d 11h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8314d 19h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8316d 13h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8318d 12h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8327d 19h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8328d 12h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8329d 08h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8383d 13h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8384d 08h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8384d 20h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8385d 13h	/uart16550/trunk/rtl/verilog/