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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 44

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Rev Log message Author Age Path
44 fixed more typo bugs gorban 8407d 10h /uart16550/trunk/rtl/verilog/
43 lsr1r error fixed. mohor 8407d 17h /uart16550/trunk/rtl/verilog/
42 ti_int_pnd error fixed. mohor 8407d 17h /uart16550/trunk/rtl/verilog/
41 ti_int_d error fixed. mohor 8407d 17h /uart16550/trunk/rtl/verilog/
40 Synthesis bugs fixed. Some other minor changes gorban 8409d 19h /uart16550/trunk/rtl/verilog/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8411d 17h /uart16550/trunk/rtl/verilog/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8412d 14h /uart16550/trunk/rtl/verilog/
36 no message mohor 8417d 22h /uart16550/trunk/rtl/verilog/
35 Fixes to break and timeout conditions gorban 8419d 16h /uart16550/trunk/rtl/verilog/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8421d 15h /uart16550/trunk/rtl/verilog/
33 Small synopsis fixes gorban 8430d 22h /uart16550/trunk/rtl/verilog/
32 Changes data_out to be synchronous again as it should have been. gorban 8431d 15h /uart16550/trunk/rtl/verilog/
31 small fix gorban 8432d 11h /uart16550/trunk/rtl/verilog/
30 Modified port names again gorban 8486d 16h /uart16550/trunk/rtl/verilog/
29 Things connected to parity changed.
Clock devider changed.		 mohor 8487d 11h /uart16550/trunk/rtl/verilog/
28 FIFO was not cleared after the data was read bug fixed. mohor 8487d 23h /uart16550/trunk/rtl/verilog/
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8488d 16h /uart16550/trunk/rtl/verilog/

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