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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8262d 00h /uart16550/trunk/rtl/verilog/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8263d 01h /uart16550/trunk/rtl/verilog/
44 fixed more typo bugs gorban 8277d 00h /uart16550/trunk/rtl/verilog/
43 lsr1r error fixed. mohor 8277d 07h /uart16550/trunk/rtl/verilog/
42 ti_int_pnd error fixed. mohor 8277d 07h /uart16550/trunk/rtl/verilog/
41 ti_int_d error fixed. mohor 8277d 07h /uart16550/trunk/rtl/verilog/
40 Synthesis bugs fixed. Some other minor changes gorban 8279d 10h /uart16550/trunk/rtl/verilog/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8281d 07h /uart16550/trunk/rtl/verilog/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8282d 04h /uart16550/trunk/rtl/verilog/
36 no message mohor 8287d 12h /uart16550/trunk/rtl/verilog/
35 Fixes to break and timeout conditions gorban 8289d 07h /uart16550/trunk/rtl/verilog/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8291d 05h /uart16550/trunk/rtl/verilog/
33 Small synopsis fixes gorban 8300d 12h /uart16550/trunk/rtl/verilog/
32 Changes data_out to be synchronous again as it should have been. gorban 8301d 06h /uart16550/trunk/rtl/verilog/
31 small fix gorban 8302d 02h /uart16550/trunk/rtl/verilog/
30 Modified port names again gorban 8356d 07h /uart16550/trunk/rtl/verilog/
29 Things connected to parity changed.
Clock devider changed.		 mohor 8357d 01h /uart16550/trunk/rtl/verilog/
28 FIFO was not cleared after the data was read bug fixed. mohor 8357d 14h /uart16550/trunk/rtl/verilog/
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8358d 06h /uart16550/trunk/rtl/verilog/

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