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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 65

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Rev	Log message	Author	Age	Path
65	Warnings fixed (unused signals removed).	mohor	8225d 07h	/uart16550/trunk/rtl/verilog/
64	Warnings cleared.	mohor	8225d 08h	/uart16550/trunk/rtl/verilog/
63	Synplicity was having troubles with the comment.	mohor	8225d 08h	/uart16550/trunk/rtl/verilog/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8226d 07h	/uart16550/trunk/rtl/verilog/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8227d 01h	/uart16550/trunk/rtl/verilog/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8227d 06h	/uart16550/trunk/rtl/verilog/
59	MSR register fixed.	mohor	8230d 02h	/uart16550/trunk/rtl/verilog/
58	After reset modem status register MSR should be reset.	mohor	8230d 06h	/uart16550/trunk/rtl/verilog/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8231d 05h	/uart16550/trunk/rtl/verilog/
56	thre irq should be cleared only when being source of interrupt.	mohor	8231d 06h	/uart16550/trunk/rtl/verilog/
55	some synthesis bugs fixed	gorban	8231d 17h	/uart16550/trunk/rtl/verilog/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8232d 07h	/uart16550/trunk/rtl/verilog/
53	Scratch register define added.	mohor	8233d 07h	/uart16550/trunk/rtl/verilog/
52	Scratch register added	gorban	8233d 20h	/uart16550/trunk/rtl/verilog/
51	Igor fixed break condition bugs	gorban	8233d 20h	/uart16550/trunk/rtl/verilog/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8238d 01h	/uart16550/trunk/rtl/verilog/
49	committed the debug interface file	gorban	8239d 19h	/uart16550/trunk/rtl/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8240d 18h	/uart16550/trunk/rtl/verilog/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8245d 20h	/uart16550/trunk/rtl/verilog/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8246d 17h	/uart16550/trunk/rtl/verilog/

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 65

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