URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [bin/] - Rev 50

Rev	Log message	Author	Age	Path
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8280d 18h	/uart16550/trunk/sim/rtl_sim/bin/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8283d 11h	/uart16550/trunk/sim/rtl_sim/bin/
14		gorban	8396d 16h	/uart16550/trunk/sim/rtl_sim/bin/