URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [log/] - Rev 96

Rev	Log message	Author	Age	Path
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7542d 03h	/uart16550/trunk/sim/rtl_sim/log/
17	added empty directories for the required structure.	gorban	8499d 13h	/uart16550/trunk/sim/rtl_sim/log/