URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] - Rev 22

Rev	Log message	Author	Age	Path
22	Removed old stimuli data file, created by perl script	hasw	5416d 17h	/uart16750/trunk/
21	Updated simulation files	hasw	5416d 17h	/uart16750/trunk/
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5546d 15h	/uart16750/trunk/
17	New directory structure.	root	5563d 00h	/uart16750/trunk/
16	UART16750: Added example project	hasw	5583d 12h	/trunk/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5592d 14h	/trunk/
14	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5593d 16h	/trunk/
13	UART16750: Added automatic flow control	hasw	5606d 17h	/trunk/
12	UART16750: Updated stimuli script with automatic flow control tests	hasw	5606d 17h	/trunk/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5606d 17h	/trunk/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5606d 18h	/trunk/
9	Registered control line outputs	hasw	5615d 19h	/trunk/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5615d 19h	/trunk/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5617d 00h	/trunk/
6	THR empty interrupt register connected to RST	hasw	5617d 00h	/trunk/
5	Removed old component	hasw	5617d 19h	/trunk/
4	Removed swap file	hasw	5617d 20h	/trunk/
2	Imported sources	hasw	5617d 20h	/trunk/
1	Standard project directories initialized by cvs2svn.		5617d 20h	/trunk/