URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [rtl/] [vhdl/] - Rev 25

Rev	Log message	Author	Age	Path
24	Inverted low active outputs when RST is active	hasw	5060d 14h	/uart16750/trunk/rtl/vhdl/
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5554d 15h	/uart16750/trunk/rtl/vhdl/
17	New directory structure.	root	5571d 01h	/uart16750/trunk/rtl/vhdl/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5600d 15h	/uart16750/trunk/rtl/vhdl/
13	UART16750: Added automatic flow control	hasw	5614d 17h	/uart16750/trunk/rtl/vhdl/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5614d 18h	/uart16750/trunk/rtl/vhdl/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5614d 18h	/uart16750/trunk/rtl/vhdl/
9	Registered control line outputs	hasw	5623d 19h	/uart16750/trunk/rtl/vhdl/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5623d 19h	/uart16750/trunk/rtl/vhdl/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5625d 00h	/uart16750/trunk/rtl/vhdl/
6	THR empty interrupt register connected to RST	hasw	5625d 01h	/uart16750/trunk/rtl/vhdl/
5	Removed old component	hasw	5625d 19h	/uart16750/trunk/rtl/vhdl/
2	Imported sources	hasw	5625d 20h	/uart16750/trunk/rtl/vhdl/