URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [rtl/] [vhdl/] - Rev 8

Rev	Log message	Author	Age	Path
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5681d 13h	/uart16750/trunk/rtl/vhdl/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5682d 17h	/uart16750/trunk/rtl/vhdl/
6	THR empty interrupt register connected to RST	hasw	5682d 18h	/uart16750/trunk/rtl/vhdl/
5	Removed old component	hasw	5683d 12h	/uart16750/trunk/rtl/vhdl/
2	Imported sources	hasw	5683d 13h	/uart16750/trunk/rtl/vhdl/