URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] - Rev 10

Rev	Log message	Author	Age	Path
10	VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	smuller	4589d 03h	/uart2bus/
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4590d 14h	/uart2bus/
8	Updated core description document to include Lattice device synthesis results.	motilito	4811d 19h	/uart2bus/
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4833d 04h	/uart2bus/
6	Commit VHDL description source with basic test benches	smuller	5082d 13h	/uart2bus/
5	Add structure for VHDL (verilog similar tree).	smuller	5094d 07h	/uart2bus/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5189d 05h	/uart2bus/
3		motilito	5235d 11h	/uart2bus/
2	Uploaded the initial project version.	motilito	5235d 12h	/uart2bus/
1	The project and the structure was created	root	5238d 06h	/uart2bus/