URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] - Rev 6

Rev	Log message	Author	Age	Path
6	Commit VHDL description source with basic test benches	smuller	5081d 12h	/uart2bus/trunk/
5	Add structure for VHDL (verilog similar tree).	smuller	5093d 06h	/uart2bus/trunk/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5188d 04h	/uart2bus/trunk/
3		motilito	5234d 10h	/uart2bus/trunk/
2	Uploaded the initial project version.	motilito	5234d 11h	/uart2bus/trunk/
1	The project and the structure was created	root	5237d 05h	/uart2bus/trunk/