URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] - Rev 13

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4482d 19h	/uart2bus/trunk/verilog/
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4577d 20h	/uart2bus/trunk/verilog/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5176d 10h	/uart2bus/trunk/verilog/
3		motilito	5222d 16h	/uart2bus/trunk/verilog/
2	Uploaded the initial project version.	motilito	5222d 18h	/uart2bus/trunk/verilog/