URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4683d 03h	/uart2bus/trunk/verilog/bench/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5376d 18h	/uart2bus/trunk/verilog/bench/
2	Uploaded the initial project version.	motilito	5423d 01h	/uart2bus/trunk/verilog/bench/