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[/] [uart_fpga_slow_control/] - Rev 20

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20 MODIFIED: block diagram with new namings for uart din and dout aborga 4657d 00h /uart_fpga_slow_control/
19 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments		 aborga 4657d 00h /uart_fpga_slow_control/
18 MODIFIED: removed unnecessary libraries aborga 4657d 20h /uart_fpga_slow_control/
17 DELETED: useless package folder aborga 4657d 22h /uart_fpga_slow_control/
16 MODIFIED: added

uart_rst_i : in std_logic;
uart_leds_o : out std_logic_vector(7 downto 0);

in the entity declaration		 aborga 4657d 22h /uart_fpga_slow_control/
15 UPDATED: email address aborga 4659d 21h /uart_fpga_slow_control/
14 ADDED: backup of the project description aborga 4660d 13h /uart_fpga_slow_control/
13 UDATED: simple documentation aborga 4660d 15h /uart_fpga_slow_control/
12 ADDED: original documentation of the UART_16550 core by LeFevre aborga 4660d 15h /uart_fpga_slow_control/
11 ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram
1) pdf format
2) Microsoft visio source file (sorry...)		 aborga 4660d 15h /uart_fpga_slow_control/
10 MODIFIED: added further description and examples aborga 4660d 21h /uart_fpga_slow_control/
9 ADDED: HowToSVN.txt to handle repositories with windows Tortoise SVN aborga 4660d 22h /uart_fpga_slow_control/
8 ADDED: some more documentation

1) screenshot of a full read and write sequence with questasim
2) example hex commands to be sent via RealTerm		 aborga 4660d 22h /uart_fpga_slow_control/
7 MODIFIED: line 359 baudrate set aborga 4660d 23h /uart_fpga_slow_control/
6 CREATED: how to change baudrate text file aborga 4660d 23h /uart_fpga_slow_control/
5 aborga 4660d 23h /uart_fpga_slow_control/
4 DELETED: moved to a code folder aborga 4660d 23h /uart_fpga_slow_control/
3 CREATED: first code upload! :) aborga 4660d 23h /uart_fpga_slow_control/
2 CREATED: first code upload! :) aborga 4660d 23h /uart_fpga_slow_control/
1 The project and the structure was created root 4661d 00h /uart_fpga_slow_control/

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