URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] - Rev 15

Rev	Log message	Author	Age	Path
15	UPDATED: email address	aborga	4674d 03h	/uart_fpga_slow_control/trunk/
14	ADDED: backup of the project description	aborga	4674d 19h	/uart_fpga_slow_control/trunk/
13	UDATED: simple documentation	aborga	4674d 21h	/uart_fpga_slow_control/trunk/
12	ADDED: original documentation of the UART_16550 core by LeFevre	aborga	4674d 21h	/uart_fpga_slow_control/trunk/
11	ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram 1) pdf format 2) Microsoft visio source file (sorry...)	aborga	4674d 22h	/uart_fpga_slow_control/trunk/
10	MODIFIED: added further description and examples	aborga	4675d 04h	/uart_fpga_slow_control/trunk/
9	ADDED: HowToSVN.txt to handle repositories with windows Tortoise SVN	aborga	4675d 04h	/uart_fpga_slow_control/trunk/
8	ADDED: some more documentation 1) screenshot of a full read and write sequence with questasim 2) example hex commands to be sent via RealTerm	aborga	4675d 05h	/uart_fpga_slow_control/trunk/
7	MODIFIED: line 359 baudrate set	aborga	4675d 05h	/uart_fpga_slow_control/trunk/
6	CREATED: how to change baudrate text file	aborga	4675d 05h	/uart_fpga_slow_control/trunk/
5		aborga	4675d 06h	/uart_fpga_slow_control/trunk/
4	DELETED: moved to a code folder	aborga	4675d 06h	/uart_fpga_slow_control/trunk/
3	CREATED: first code upload! :)	aborga	4675d 06h	/uart_fpga_slow_control/trunk/
2	CREATED: first code upload! :)	aborga	4675d 06h	/uart_fpga_slow_control/trunk/
1	The project and the structure was created	root	4675d 07h	/uart_fpga_slow_control/trunk/