OpenCores
URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 ADDED: software folder with python script (simple but stable) and .bat file to load RealTerm with parameters (extremely unstable) aborga 4576d 03h /uart_fpga_slow_control/trunk/
27 MODIFIED: small description improvement aborga 4583d 03h /uart_fpga_slow_control/trunk/
26 ADDED: screenshot of the simulation output with tb_uart_control.vhd (project tested with modelsim 6) aborga 4657d 00h /uart_fpga_slow_control/trunk/
25 MODIFIED: small comment improvement aborga 4657d 03h /uart_fpga_slow_control/trunk/
24 UPDATED: added folder testbenches with a generic tb_UART_control.vhd testbench aborga 4657d 03h /uart_fpga_slow_control/trunk/
23 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4657d 04h /uart_fpga_slow_control/trunk/
22 aborga 4657d 05h /uart_fpga_slow_control/trunk/
21 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4657d 05h /uart_fpga_slow_control/trunk/
20 MODIFIED: block diagram with new namings for uart din and dout aborga 4657d 05h /uart_fpga_slow_control/trunk/
19 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4657d 05h /uart_fpga_slow_control/trunk/
18 MODIFIED: removed unnecessary libraries aborga 4658d 02h /uart_fpga_slow_control/trunk/
17 DELETED: useless package folder aborga 4658d 03h /uart_fpga_slow_control/trunk/
16 MODIFIED: added

uart_rst_i : in std_logic;
uart_leds_o : out std_logic_vector(7 downto 0);

in the entity declaration
aborga 4658d 03h /uart_fpga_slow_control/trunk/
15 UPDATED: email address aborga 4660d 02h /uart_fpga_slow_control/trunk/
14 ADDED: backup of the project description aborga 4660d 18h /uart_fpga_slow_control/trunk/
13 UDATED: simple documentation aborga 4660d 20h /uart_fpga_slow_control/trunk/
12 ADDED: original documentation of the UART_16550 core by LeFevre aborga 4660d 20h /uart_fpga_slow_control/trunk/
11 ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram
1) pdf format
2) Microsoft visio source file (sorry...)
aborga 4660d 20h /uart_fpga_slow_control/trunk/
10 MODIFIED: added further description and examples aborga 4661d 03h /uart_fpga_slow_control/trunk/
9 ADDED: HowToSVN.txt to handle repositories with windows Tortoise SVN aborga 4661d 03h /uart_fpga_slow_control/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.