URL https://opencores.org/ocsvn/usb/usb/trunk

Subversion Repositories usb

[/] [usb/] [trunk/] [rtl/] [verilog/] - Rev 19

Rev	Log message	Author	Age	Path
19		root	5512d 19h	/usb/trunk/rtl/verilog/
15	New directory structure.	root	5569d 00h	/usb/trunk/rtl/verilog/
14	Fixed Resume signaling and initial attachment	rudi	7515d 03h	/usb/trunk/rtl/verilog/
13	- Disabling bit stuffing and NRZI encoding during speed negotiation - Now the core can send zero size packets - Fixed register addresses for some of the higher endpoints (conversion between decimal/hex was wrong) - The core now does properly evaluate the function address to determine if the packet was intended for it. - Various other minor bugs and typos	rudi	7540d 07h	/usb/trunk/rtl/verilog/
11	- Fixed previous fix (brocke something else ...) - Majore Synthesis cleanup	rudi	8251d 22h	/usb/trunk/rtl/verilog/
10	- Fixed several interrupt and error condition reporting bugs	rudi	8253d 07h	/usb/trunk/rtl/verilog/
9	Changed reset to be active high async.	rudi	8293d 09h	/usb/trunk/rtl/verilog/
8	Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ...	rudi	8294d 01h	/usb/trunk/rtl/verilog/
7	Fixed TxValid handling bug.	rudi	8297d 19h	/usb/trunk/rtl/verilog/
6	Fixed a problem that would sometimes prevent the core to come out of reset and immediately be operational ...	rudi	8303d 21h	/usb/trunk/rtl/verilog/
5	Fixed crc5 checking.	rudi	8306d 18h	/usb/trunk/rtl/verilog/
4	- Changed IO names to be more clear. - Uniquifyed define names to be core specific.	rudi	8338d 01h	/usb/trunk/rtl/verilog/
2	1) Reorganized directory structure	rudi	8345d 04h	/usb/trunk/rtl/verilog/