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[/] [usb_dongle_fpga/] [tags/] [version_1_5/] - Rev 53

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Rev Log message Author Age Path
53 New directory structure. root 5588d 22h /usb_dongle_fpga/tags/version_1_5/
45 This commit was manufactured by cvs2svn to create tag 'version_1_5'. 5914d 23h /tags/version_1_5/
36 Initial commit of EPCS1 (FPGA configuration memory) programmet to update dongle firmware nuubik 5949d 22h /trunk/
35 Fixed postcode nibbles swapped issue added D0 D11 commands for IO port 0x88
(enable/disable memory reads)		 nuubik 5949d 22h /trunk/
34 For download of v5 dongle tool and manual nuubik 5951d 23h /trunk/
33 For download of v5 web release nuubik 5952d 00h /trunk/
32 For download of v5 datasheet nuubik 5952d 00h /trunk/
31 Newest available schematic nuubik 5952d 17h /trunk/
30 Fixed some typos in document nuubik 5952d 17h /trunk/
29 Added link to cheap ($40) ByteBlaster clone cable to update notice and fix'ed help typo nuubik 5952d 17h /trunk/
28 Quartus project files for HW code 5 project files nuubik 5953d 18h /trunk/
27 Initial commit of post code logger block and fifo used in the logger nuubik 5953d 18h /trunk/
26 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added post code logger block and LPC IO write flow control and flash lock when flash is programmed		 nuubik 5953d 18h /trunk/
25 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added 64K byte block read when read length is 0		 nuubik 5953d 18h /trunk/
24 Added changes for new dongle HW code 5 features nuubik 5953d 18h /trunk/
23 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed.
Forced serial port to hw flow control mode.
Added support for new dongle HW code 5 to support fast read and fast write modes		 nuubik 5953d 18h /trunk/
22 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed nuubik 5953d 18h /trunk/
20 Fix'ed TAR cycle second part this is not critical update nuubik 5966d 21h /trunk/
19 Fix'ed cycle type init code copy/pase mistake nuubik 5966d 23h /trunk/
18 Fixed in reset init of some trigers (this should not have generated extra hardware in FPGA but just to be on the safe side) nuubik 5967d 22h /trunk/

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