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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] - Rev 40

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Rev Log message Author Age Path
40 New directory structure. root 5591d 19h /usbhostslave/trunk/RTL/hostController/
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5789d 05h /usbhostslave/trunk/RTL/hostController/
34 *** empty log message *** sfielding 6467d 23h /usbhostslave/trunk/RTL/hostController/
22 Release 1.2 sfielding 6470d 02h /usbhostslave/trunk/RTL/hostController/
20 Fixed RX clock recovery bug, and RX time out bug sfielding 6701d 00h /usbhostslave/trunk/RTL/hostController/
18 Added dual clock, fixed slave bug, added reset register sfielding 6805d 15h /usbhostslave/trunk/RTL/hostController/
16 Added bus access to SOF timer sfielding 6944d 17h /usbhostslave/trunk/RTL/hostController/
14 Added LS keep alive, fixed clock recovery bug sfielding 7054d 01h /usbhostslave/trunk/RTL/hostController/
12 try again sfielding 7084d 16h /usbhostslave/trunk/RTL/hostController/
9 Fixed bus turn-around problems, added version number sfielding 7101d 16h /usbhostslave/trunk/RTL/hostController/
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7121d 15h /usbhostslave/trunk/RTL/hostController/
5 Removed html documentation sfielding 7134d 15h /usbhostslave/trunk/RTL/hostController/
2 Created sfielding 7203d 02h /usbhostslave/trunk/RTL/hostController/

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