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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [slaveController/] - Rev 40

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Rev Log message Author Age Path
40 New directory structure. root 5580d 20h /usbhostslave/trunk/RTL/slaveController/
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5778d 06h /usbhostslave/trunk/RTL/slaveController/
34 *** empty log message *** sfielding 6457d 00h /usbhostslave/trunk/RTL/slaveController/
22 Release 1.2 sfielding 6459d 02h /usbhostslave/trunk/RTL/slaveController/
20 Fixed RX clock recovery bug, and RX time out bug sfielding 6690d 01h /usbhostslave/trunk/RTL/slaveController/
18 Added dual clock, fixed slave bug, added reset register sfielding 6794d 15h /usbhostslave/trunk/RTL/slaveController/
14 Added LS keep alive, fixed clock recovery bug sfielding 7043d 02h /usbhostslave/trunk/RTL/slaveController/
12 try again sfielding 7073d 17h /usbhostslave/trunk/RTL/slaveController/
9 Fixed bus turn-around problems, added version number sfielding 7090d 17h /usbhostslave/trunk/RTL/slaveController/
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7110d 16h /usbhostslave/trunk/RTL/slaveController/
5 Removed html documentation sfielding 7123d 16h /usbhostslave/trunk/RTL/slaveController/
2 Created sfielding 7192d 02h /usbhostslave/trunk/RTL/slaveController/

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