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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

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[/] [usbhostslave/] [trunk/] [bench/] - Rev 43

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Rev Log message Author Age Path
40 New directory structure. root 5726d 03h /usbhostslave/trunk/bench/
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5923d 12h /trunk/bench/

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