URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] - Rev 32

Rev	Log message	Author	Age	Path
32	fixed SYN directives	marcus.erlandsson	4981d 19h	/versatile_fifo/trunk/rtl/
31	port map	unneback	5052d 12h	/versatile_fifo/trunk/rtl/
30	port map	unneback	5052d 13h	/versatile_fifo/trunk/rtl/
29	ACTEL syn define	unneback	5060d 10h	/versatile_fifo/trunk/rtl/
28	ACTEL async dual way FIFO	unneback	5067d 20h	/versatile_fifo/trunk/rtl/
27	initial commit, dual way simplex FIFO	unneback	5068d 11h	/versatile_fifo/trunk/rtl/
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5068d 11h	/versatile_fifo/trunk/rtl/
25	DFF SR as separate logic	unneback	5208d 07h	/versatile_fifo/trunk/rtl/
24	updated fifo interfaces with re/rd and we/wr	unneback	5208d 21h	/versatile_fifo/trunk/rtl/
23		unneback	5211d 10h	/versatile_fifo/trunk/rtl/
22	async fifo with multiple queues	unneback	5211d 10h	/versatile_fifo/trunk/rtl/
21	added DFF SR	unneback	5225d 08h	/versatile_fifo/trunk/rtl/
18	ADDR and DATA width set to 8 resp 32	unneback	5227d 11h	/versatile_fifo/trunk/rtl/
17	based on updated versatile counter	unneback	5231d 09h	/versatile_fifo/trunk/rtl/
16	changed power of two style	unneback	5494d 19h	/versatile_fifo/trunk/rtl/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5498d 13h	/versatile_fifo/trunk/rtl/
13	adr update	unneback	5543d 22h	/versatile_fifo/trunk/rtl/
12	no mux on dual port mem read	unneback	5556d 15h	/versatile_fifo/trunk/rtl/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5556d 17h	/versatile_fifo/trunk/rtl/
10	rptr2	unneback	5556d 19h	/versatile_fifo/trunk/rtl/