URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] - Rev 22

Rev	Log message	Author	Age	Path
22	async fifo with multiple queues	unneback	5252d 23h	/versatile_fifo/trunk/rtl/verilog/
21	added DFF SR	unneback	5266d 21h	/versatile_fifo/trunk/rtl/verilog/
18	ADDR and DATA width set to 8 resp 32	unneback	5269d 00h	/versatile_fifo/trunk/rtl/verilog/
17	based on updated versatile counter	unneback	5272d 22h	/versatile_fifo/trunk/rtl/verilog/
16	changed power of two style	unneback	5536d 08h	/versatile_fifo/trunk/rtl/verilog/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5540d 02h	/versatile_fifo/trunk/rtl/verilog/
13	adr update	unneback	5585d 11h	/versatile_fifo/trunk/rtl/verilog/
12	no mux on dual port mem read	unneback	5598d 04h	/versatile_fifo/trunk/rtl/verilog/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5598d 06h	/versatile_fifo/trunk/rtl/verilog/
10	rptr2	unneback	5598d 08h	/versatile_fifo/trunk/rtl/verilog/
9		unneback	5604d 03h	/versatile_fifo/trunk/rtl/verilog/
8		unneback	5604d 03h	/versatile_fifo/trunk/rtl/verilog/
7		unneback	5604d 03h	/versatile_fifo/trunk/rtl/verilog/
6		unneback	5604d 06h	/versatile_fifo/trunk/rtl/verilog/
5	async compare for fifo full and empty	unneback	5604d 06h	/versatile_fifo/trunk/rtl/verilog/
4		unneback	5604d 11h	/versatile_fifo/trunk/rtl/verilog/
2		unneback	5604d 11h	/versatile_fifo/trunk/rtl/verilog/