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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 26

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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4931d 14h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4932d 04h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4933d 11h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4934d 02h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4934d 07h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4935d 03h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4936d 15h /versatile_library/trunk/rtl/verilog/
17 unneback 5000d 04h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 5006d 12h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 5006d 17h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 5006d 18h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 5007d 14h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 5008d 05h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 5010d 04h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 5010d 04h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 5010d 05h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 5023d 05h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 5023d 06h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 5027d 10h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added		 unneback 5030d 05h /versatile_library/trunk/rtl/verilog/

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