OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 27

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
27 added sync simplex FIFO unneback 4950d 00h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4950d 01h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4950d 15h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4951d 22h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4952d 13h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4952d 18h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4953d 14h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4955d 02h /versatile_library/trunk/rtl/verilog/
17 unneback 5018d 15h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 5024d 23h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 5025d 04h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 5025d 05h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 5026d 01h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 5026d 16h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 5028d 15h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 5028d 15h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 5028d 16h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 5041d 16h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 5041d 17h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 5045d 21h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.