URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 12

Rev	Log message	Author	Age	Path
12	Minor update of whishbone FSMs in TB	mikaeljf	5342d 00h	/versatile_mem_ctrl/
11	Initial version with support for DDR	mikaeljf	5342d 12h	/versatile_mem_ctrl/
10		unneback	5369d 20h	/versatile_mem_ctrl/
9	testbench	unneback	5369d 20h	/versatile_mem_ctrl/
8		unneback	5465d 16h	/versatile_mem_ctrl/
7		unneback	5465d 16h	/versatile_mem_ctrl/
6		unneback	5465d 16h	/versatile_mem_ctrl/
5	pass initial testing	unneback	5465d 17h	/versatile_mem_ctrl/
4		unneback	5466d 19h	/versatile_mem_ctrl/
3		unneback	5466d 22h	/versatile_mem_ctrl/
2	initial	unneback	5472d 20h	/versatile_mem_ctrl/
1	The project was created and the structure was created	root	5472d 20h	/versatile_mem_ctrl/