URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5361d 12h	/versatile_mem_ctrl/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5361d 15h	/versatile_mem_ctrl/
12	Minor update of whishbone FSMs in TB	mikaeljf	5371d 16h	/versatile_mem_ctrl/
11	Initial version with support for DDR	mikaeljf	5372d 04h	/versatile_mem_ctrl/
10		unneback	5399d 12h	/versatile_mem_ctrl/
9	testbench	unneback	5399d 12h	/versatile_mem_ctrl/
8		unneback	5495d 08h	/versatile_mem_ctrl/
7		unneback	5495d 08h	/versatile_mem_ctrl/
6		unneback	5495d 08h	/versatile_mem_ctrl/
5	pass initial testing	unneback	5495d 09h	/versatile_mem_ctrl/
4		unneback	5496d 12h	/versatile_mem_ctrl/
3		unneback	5496d 14h	/versatile_mem_ctrl/
2	initial	unneback	5502d 12h	/versatile_mem_ctrl/
1	The project was created and the structure was created	root	5502d 12h	/versatile_mem_ctrl/