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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 19

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Rev Log message Author Age Path
19 Added do-file for Modelsim waveform viewer. mikaeljf 5236d 16h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5237d 13h /versatile_mem_ctrl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5240d 12h /versatile_mem_ctrl/
16 Added fizzim.pl mikaeljf 5240d 13h /versatile_mem_ctrl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5241d 13h /versatile_mem_ctrl/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5331d 15h /versatile_mem_ctrl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5331d 18h /versatile_mem_ctrl/
12 Minor update of whishbone FSMs in TB mikaeljf 5341d 19h /versatile_mem_ctrl/
11 Initial version with support for DDR mikaeljf 5342d 07h /versatile_mem_ctrl/
10 unneback 5369d 15h /versatile_mem_ctrl/
9 testbench unneback 5369d 15h /versatile_mem_ctrl/
8 unneback 5465d 11h /versatile_mem_ctrl/
7 unneback 5465d 11h /versatile_mem_ctrl/
6 unneback 5465d 11h /versatile_mem_ctrl/
5 pass initial testing unneback 5465d 12h /versatile_mem_ctrl/
4 unneback 5466d 15h /versatile_mem_ctrl/
3 unneback 5466d 17h /versatile_mem_ctrl/
2 initial unneback 5472d 15h /versatile_mem_ctrl/
1 The project was created and the structure was created root 5472d 15h /versatile_mem_ctrl/

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