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[/] [versatile_mem_ctrl/] - Rev 28

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Rev Log message Author Age Path
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5209d 00h /versatile_mem_ctrl/
27 unneback 5212d 16h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5214d 15h /versatile_mem_ctrl/
25 unneback 5214d 17h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5215d 05h /versatile_mem_ctrl/
23 Removed redundant code. mikaeljf 5222d 21h /versatile_mem_ctrl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5224d 17h /versatile_mem_ctrl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5228d 20h /versatile_mem_ctrl/
20 Minor update of sdc-file. mikaeljf 5230d 22h /versatile_mem_ctrl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5237d 02h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5237d 23h /versatile_mem_ctrl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5240d 22h /versatile_mem_ctrl/
16 Added fizzim.pl mikaeljf 5240d 23h /versatile_mem_ctrl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5241d 23h /versatile_mem_ctrl/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5332d 01h /versatile_mem_ctrl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5332d 04h /versatile_mem_ctrl/
12 Minor update of whishbone FSMs in TB mikaeljf 5342d 05h /versatile_mem_ctrl/
11 Initial version with support for DDR mikaeljf 5342d 17h /versatile_mem_ctrl/
10 unneback 5370d 00h /versatile_mem_ctrl/
9 testbench unneback 5370d 01h /versatile_mem_ctrl/

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