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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 29

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Rev Log message Author Age Path
29 Adapted the test bench to the new wishbone interface. mikaeljf 5207d 17h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5207d 19h /versatile_mem_ctrl/
27 unneback 5211d 11h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5213d 10h /versatile_mem_ctrl/
25 unneback 5213d 12h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5214d 00h /versatile_mem_ctrl/
23 Removed redundant code. mikaeljf 5221d 16h /versatile_mem_ctrl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5223d 12h /versatile_mem_ctrl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5227d 15h /versatile_mem_ctrl/
20 Minor update of sdc-file. mikaeljf 5229d 17h /versatile_mem_ctrl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5235d 21h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5236d 18h /versatile_mem_ctrl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5239d 17h /versatile_mem_ctrl/
16 Added fizzim.pl mikaeljf 5239d 18h /versatile_mem_ctrl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5240d 18h /versatile_mem_ctrl/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5330d 20h /versatile_mem_ctrl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5330d 23h /versatile_mem_ctrl/
12 Minor update of whishbone FSMs in TB mikaeljf 5341d 00h /versatile_mem_ctrl/
11 Initial version with support for DDR mikaeljf 5341d 11h /versatile_mem_ctrl/
10 unneback 5368d 19h /versatile_mem_ctrl/

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