URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 33

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
33	work for limited test case, no cke inhibit for fifo empty	unneback	5194d 20h	/versatile_mem_ctrl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5198d 00h	/versatile_mem_ctrl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5199d 17h	/versatile_mem_ctrl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5199d 17h	/versatile_mem_ctrl/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5203d 17h	/versatile_mem_ctrl/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5203d 19h	/versatile_mem_ctrl/
27		unneback	5207d 10h	/versatile_mem_ctrl/
26	compiles OK, not simulated	unneback	5209d 09h	/versatile_mem_ctrl/
25		unneback	5209d 12h	/versatile_mem_ctrl/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5209d 23h	/versatile_mem_ctrl/
23	Removed redundant code.	mikaeljf	5217d 16h	/versatile_mem_ctrl/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5219d 12h	/versatile_mem_ctrl/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5223d 15h	/versatile_mem_ctrl/
20	Minor update of sdc-file.	mikaeljf	5225d 17h	/versatile_mem_ctrl/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5231d 21h	/versatile_mem_ctrl/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5232d 18h	/versatile_mem_ctrl/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5235d 17h	/versatile_mem_ctrl/
16	Added fizzim.pl	mikaeljf	5235d 18h	/versatile_mem_ctrl/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5236d 18h	/versatile_mem_ctrl/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5326d 20h	/versatile_mem_ctrl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 33

Filtering Options